As is well known, considerable effort is spent in academia and industry towards developing techniques enabling the detection of defects in wafers before their cleavage into distinct dies, capsulation and subsequent distribution to the marketplace in the form of chips. In recent years, defect detection has been improved by techniques for classifying defects into distinct defect types. These techniques not only allow identification of defective wafers so as to increase the yield, but also to provide some information on the cause of the defects. The production stage can then be reconfigured or modified in order to produce a better wafer series.
A conventional method for defect classification called Automatic Defect Classification applying certain algorithm to the defect image taken by a CCD camera to attempt and classify the defect. The algorithm is typically implemented by a review tool, such as a review scanning electron microscope (SEM). However, the review tool is often different from the inspection tool used to locate the defects. Thus, in order to classify the defects, the system first has to scan the entire wafer with the inspection tool, send the wafer to the review tool and re-visit the suspected sites identified during the inspection mode, take a magnified image of the defect and a reference site, and only then apply the ADC algorithm to classify the defect. In addition, the system uses only a single image of the defect from a single perspective.
Currently, defect classification is often performed by comparing a defect and reference SEM image and using various aspects of the differences to generate properties of the defect in relation to the reference that would allow classification of the defect based on a known training set. Generally ADC based on a training set is only trying to group based on defect type. One drawback to this method is that the classification is only based on comparison to prior defects. The system therefore has no knowledge of the actual design of the devices to be formed on the wafer and therefore might bin two defects of the same type as the same criticality even though they occur at two different locations on the device.
NGR2100 of NanoGeometry Research is a large scale inspection tool, which generates patchwork image of entire die using SEM and compares image to design information to find problems with design or process. However, the test is performed on a test wafer, not production wafer and the scanning process takes a significant period of time, e.g., about one day.
Thus, there is a need in the art for improved defect detection and classification. It is within this context that embodiments of the present invention arise.